The present invention relates to a semiconductor device having a protecting circuit for protecting an internal circuit from a surge voltage.
Conventionally, an input circuit or input/output circuit connected to an internal circuit has been provided with a protecting circuit for protecting the gate of, e.g., a MOS transistor composing the internal circuit. The protecting circuit is composed of a resistor, diode, transistor, or the like.
A description will be given below to an example of a conventional protecting circuit with reference to FIG. 7.
As shown in FIG. 7, a p-type semiconductor substrate 1 is formed with first and second n-type high-concentration layers 2 and 3 which extend in spaced relation to each other in parallel with the main surface of the semiconductor substrate. The first and second n-type high-concentration layers 2 and 3 are isolated from each other by a field oxide film 4. An interlayer insulating film 5 is formed over the first and second n-type high-concentration layers 2 and 3. A first metal layer 6 extending in parallel with the first n-type high-concentration layer 2 and a second metal layer 7 extending in parallel with the second n-type high-concentration layer 3 are formed on the interlayer insulating film 5. The first metal layer 6 is connected not only to an input pad INP for inputting a signal to an input circuit or input/output circuit but also to the first n-type high-concentration layer 2 via contacts. The second metal layer 7 has both end portions connected to a reference voltage pad VSP for supplying a reference voltage Vss and has a center portion connected to the second n-type high-concentration layer 3.
A description will be given below to the operation of the conventional protecting circuit.
If a positive surge voltage is applied to the protecting circuit from the input pad INP, a PN junction between the semiconductor substrate 1 and the first n-type high-concentration layer 2 connected to the input pad INP via the first metal layer 6 breaks down, so that holes flow into the p-type semiconductor substrate 1. When the holes flow into the p-type semiconductor substrate 1, a potential at the region of the p-type semiconductor substrate 1 adjacent the first n-type high-concentration layer 2 increases locally. As a result, a parasitic bipolar transistor QP operates to allow a bipolar current to flow between the input pad INP and the reference voltage pad VSP, which allows a surge current to flow to the reference voltage pad VSP.
On the other hand, if a negative surge voltage is applied to the protecting circuit from the input pad INP, the p-type semiconductor substrate 1 and the first n-type high-concentration layer 2 are forward biased. Accordingly, a forward current for a diode flows between the reference voltage pad VSP and the input pad INP, which allows a surge current to flow to the input pad INP.
In accordance with the aforesaid principle of operation, the protecting circuit promptly absorbs the surge voltage to prevent a high voltage from being applied to an internal circuit, so that damage of the internal elements of a semiconductor device is prevented.
However, since the regions of the first n-type high-concentration layer 2 immediately underlying the connection regions between the first metal layer 6 and the first n-type high-concentration layer 2 is low in impedance, if the positive surge voltage is applied to the input pad INP, a breakdown current is localized to the regions of the first n-type high-concentration layer 2 immediately underlying the connection regions between the first metal layer 6 and the first n-type high-concentration layer 2. This raises the possibility of damage of the PN junction between the first n-type high-concentration layer 2 and the p-type semiconductor substrate 1 or damage of the first n-type high-concentration layer 2 itself.
If considerations are given to a current path extending from the connection region between the first n-type high-concentration layer 2 and the first metal layer 6 to the p-type semiconductor substrate 1, the current path is shorter in length in a direction (vertical direction) perpendicular to the connection plane between the first metal layer 6 and the first n-type high-concentration layer 2 than in a direction (lateral direction) parallel to the connection plane, so that the breakdown current flows in large quantity in the direction perpendicular to the connection plane between the first metal layer 6 and the first n-type high-concentration layer 2, while the breakdown current is less likely to flow in the direction parallel to the connection plane. This prevents the parasitic bipolar transistor QP from thoroughly absorbing the surge current.
To enhance the ability of the protecting circuit to absorb the surge current, therefore, the area occupied by the first n-type high-concentration layer 2 should be increased. If the area occupied by the first n-type high-concentration layer 2 is increased, however, an input capacitance or input/output capacitance is increased and a delay time for an input signal or output signal is elongated, which causes the problem of lower operating speed of the internal circuit.